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WM8143-10 10-bit/6MSPS CCD Signal Processor
Production Data June 1998 Rev 3f
Description
The WM8143-10 integrates the analogue signal conditioning required by CCD sensors with a 10-bit ADC. The WM8143-10 requires minimal external circuitry and provides a cost-effective sensor to digital domain system solution. Each of the three analogue conditioning channels includes reset level clamp, CDS, fine offset level shifting and programmable gain amplification. The three channels are multiplexed into the ADC. The output from the ADC is fed to the output bus pins OP[9:0] via a 10/8 bit multiplexer, enabled by the OEB signal. The flexible output architecture allows ten-bit data to be accessed either on a ten-bit bus or via a time-multiplexed eight-bit bus. The WM8143-10 can be configured for pixel-by-pixel or line-by-line multiplexing operation. Reset level clamp and/or CDS features can be optionally bypassed. The device configuration is programmed either via a simple serial interface or via an eight-bit parallel interface. The serial/parallel interfaces of the WM8143-10 are control compatible with those of the WM8144-10 and WM8144-12.
Features
* * * * * * * * * * Reset level clamp Correlated double sampling (CDS) Fine offset level shifting Programmable gain amplification 10-bit ADC with maximum 6 MSPS Simple clocking scheme Control by serial or parallel interface Time multiplexed eight-bit data output mode 32 pin TQFP package Interface compatible with WM8144-10 and WM8144-12
Applications
* * * * * Flatbed scanners Sheet feed scanners Film scanners CCD sensor interfaces Contact image sensor (CIS) interfaces
Block Diagram
VRLC VRU VRT VRB VMID VSMP MCLK RLC AGND DGND DVDD AVDD
MUX TIMING CONTROL
CL VMID
RS
VS
OFFSET RINP S/H CDS 5-BIT REG 8-BIT + SIGN DAC S/H PGA
+
+
WM8143-10
VMID OFFSET
GINP S/H CDS
S/H
PGA
+
+
M U X
OEB 10-bit ADC
10/8 MUX
OP[9:0]
5-BIT REG
8-BIT + SIGN DAC
VMID
OFFSET BINP S/H CDS 5-BIT REG 8-BIT + SIGN DAC CONFIGURABLE SERIAL/PARALLEL CONTROL INTERFACE SDI / DNA SCK / RNW SEN / STB NRESET S/H PGA
+
+
VMID
Production Data datasheets contain final specifications current on publication date. Supply of products conforms to Wolfson Microelectronic's terms and conditions.
Wolfson Microelectronics
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 email: sales@wolfson.co.uk www: http://www.wolfson.co.uk
(c)1998 Wolfson Microelectronics Ltd.
WM8143-10
Pin Configuration
SEN/STB SDI/DNA VRLC VMID GINP RINP BINP OEB
Production Data
Ordering Information
DEVICE
WM8143-10CFT/V
TEMP. RANGE
0 - 70 C
o
PACKAGE
32 Pin TQFP
24
23
22
21
20
19
18
17
SCK/RNW RLC VSMP MCLK DGND nc nc DVDD
25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8
16 15 14
VRT VRB VRU AGND AVDD NRESET OP[9] OP[8]
WM8143-10
13 12 11 10 9
OP[2]
OP[3]
OP[4]
OP[5]
OP[6]
Absolute Maximum Ratings
Analogue Supply Voltage .......... AGND - 0.3V, AGND +7V Operating Temperature Range, TA .......... 0C to +70C Digital Supply Voltage ...............DGND - 0.3V, DGND +7V Storage Temperature.......................... -50C to +150C Digital Inputs .......................... DGND - 0.3V, DVDD +0.3V Lead Temperature (soldering 10 seconds) ....... +260C Digital Outputs ....................... DGND - 0.3V, DVDD +0.3V Reference Inputs ....................AGND - 0.3V, AVDD +0.3V RINP, GINP, BINP..................AGND - 0.3 V, AVDD +0.3V Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. As per JEDEC specifications A112-A and A113-A, this product requires specific storage conditions prior to surface mount assembly. It has been classified as having a Moisture Sensitivity Level of 2 and as such will be supplied in vacuum-sealed moisture barrier bags.
Recommended Operating Conditions
PARAMETER
Supply Voltage Operating Temperature Range Input Common Mode Range
OP[0]
OP[1]
OP[7]
SYMBOL
AVDD, DVDD TA VCMR
TEST CONDITIONS
MIN
4.75 0 0.5
TYP
MAX
5.25 70 4.5
UNIT
V
o
C
V
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WM8143-10
Electrical Characteristics
Test Characteristics
AVDD = DVDD = 4.75V to 5.25V, AGND = DGND = 0V ... TA = 0oC to +70oC, MCLK = 12MHz, unless otherwise stated
PARAMETER
Supply Current - Active Supply Current - Standby Digital Inputs High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance Digital Outputs High Level Output Voltage Low Level Output Voltage High Impedance Output Current Input Multiplexer CDS Mode Full Scale Input Range (VVS-VRS) Channel to Channel Gain Matching Input Video Set-up Time Input Video Hold Time Reset Video Set-up Time Reset Video Hold Time Reference String Reference Voltage - Top Reference Voltage - Bottom DAC Reference Voltage R.L.C. Switching Impedance Reset Level Clamp Options
SYMBOL
TEST CONDITIONS
MIN
TYP
100 7
MAX
140 15
UNIT
mA mA
VIH VIL IIH IIL
0.8*DVDD 0.2*DVDD 1 1 5
V V A A pF
VOH VOL IOZ
IOH = 1mA IOL= 1mA
DVDD-0.75 DGND+0.75 1
V V A
x denotes the channel selected
2 Gx
1
Vp-p % ns ns ns ns
tVSU tVH tRSU tRH CDS Mode only CDS Mode only
10 15 10 15
VRT VRB VMID
VRU = 5V VRU = 5V VRU = 5V
3.47 1.47 2.47
3.5 1.5 2.5 500
3.53 1.53 2.53
V V V
VRLC
VRU=5V Voltage set by register configuration
1.46 2.46 3.46 250 1000
1.5 2.5 3.5 500 1500
1.54 2.54 3.54 750 2000
V V V
Impedance VRT to VRB Impedance VRU to AGND 8-Bit DACs Resolution Zero Code Voltage Full Scale Voltage Error
8 VMID -20 0 VMID +20 20
Bits mV mV
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Test Characteristics
Production Data
AVDD = DVDD = 4.75V to 5.25V, AGND = DGND = 0V ... TA = 0oC to +70oC, MCLK = 12MHz, unless otherwise stated
PARAMETER
Differential Non Linearity Integral Non Linearity
SYMBOL
DNL INL
TEST CONDITIONS
MIN
TYP
0.1 0.25
MAX
0.5 1
UNIT
LSB LSB
10-bit ADC performance including CDS, PGA and Offset Functions NO MISSING CODES GUARANTEED Resolution Maximum Sampling Rate Zero Scale Transition Error Voltage at VINP AVDD = DVDD = 5V AVDD = DVDD = 5V DAC Code = 000H, AVDD = DVDD = 5V, measured relative to VRB DAC Code = 000H, AVDD = DVDD = 5V, measured relative to VRT DNL AVDD = DVDD = 5V 10 6 25 100 Bits MSPS mV
Full Scale Transition Error Voltage at VINP
25
100
mV
Differential Non Linearity PGA Gain Monotonicity Guaranteed Red Channel Max Gain Green Channel Max Gain Blue Channel Max Gain Switching Characteristics MCLK Period MCLK High MCLK Low Data Set-up Time Data Hold Time Output Propagation Delay Output Enable Time Output Disable Time Serial Interface SCK Period SCK High SCK Low SDI Set up Time SDI Hold Time Set up Time - SCK to SEN Set up Time - SEN to SCK
+1
LSB
Gr Gg Gb
Mode 1 AVDD = DVDD = 5V
7 7.5 7.5
7.5 8 8
Times Times Times
tPER tCKH tCKL tDSU tDH tPD tPZE tPEZ IOH=1mA, IOL=1mA
83.3 37.5 37.5 10 10 75 50 25
ns ns ns ns ns ns ns ns
tSPER tSCKH tSCKL tSSU tSH tSCE tSEC
83.3 37.5 37.5 10 10 20 20
ns ns ns ns ns ns ns
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Production Data
WM8143-10
Test Characteristics
AVDD = DVDD = 4.75V to 5.25V, AGND = DGND = 0V ... TA = 0oC to +70oC, MCLK = 12MHz, unless otherwise stated
PARAMETER
SEN Pulse Width Parallel Interface RNW Low to OP[9:2] Tri-state Address Setup Time to STB Low DNA Low Setup Time to STB Low Strobe Low Time Address Hold Time from STB High DNA Low Hold Time from STB High Data Setup Time to STB Low DNA High Setup Time to STB Low Data Hold Time from STB High Data High Hold Time from STB High RNW High to OP[9:2] Output
SYMBOL
tSEW
TEST CONDITIONS
MIN
50
TYP
MAX
UNIT
ns
tOPZ tASU tADLS tSTB tAH tADLH tDSU tADHS tDH tADHH tOPD 0 10 50 10 10 0 10 10 10 0
20
ns ns ns ns ns ns ns ns ns ns ns
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Pin Description
PIN
1 2 3 4 5 6 7 8 9 10 11
Production Data
NAME
OP[0] OP1] OP[2] OP[3] OP[4] OP[5] OP[6] OP[7] OP[8] OP[9] NRESET
TYPE
Digital OP Digital OP Digital IO Digital IO Digital IO Digital IO Digital IO Digital IO Digital IO Digital IO Digital IP Input 8-bit: Tri-state: Output ten-bit: Output 8-bit multiplexed:
DESCRIPTION
Tri-state digital 10-bit bi-directional bus. There are four modes: when OEB = 1 ten bit data is output from bus data output on OP[9:2] at 2 * ADC conversion rate control data is input on bits OP[9:2] in parallel mode when SCK/RNW = 0.
MSB of the output word is OP[9], LSB is OP[0] Reset input, active low. This signal forces a reset of all internal registers and selects whether serial control bus or parallel control bus is used ( see SEN/STB) Positive analogue supply (5V) Analogue ground (0V) ADC reference voltages. The ADC reference range is applied between VRT (full scale) and VRB (zero level). VRU can be used to derive optimal reference voltages from an external 5V reference Buffered mid-point of ADC reference string. Selectable analogue output voltage for RLC Blue channel input video Green channel input video Red channel input video Output tri-state control: Serial interface: Parallel interface: all outputs enabled when OEB=0 enable, active high strobe, active low
12 13 14 15 16 17 18 19 20 21 22 23
AVDD AGND VRU VRB VRT VMID VRLC BINP GINP RINP OEB SEN/STB
Analogue supply Analogue supply Analogue IP Analogue OP Analogue OP Analogue OP Analogue OP Analogue IP Analogue IP Analogue IP Digital IP Digital IP
Latched on NRESET rising edge: If low then device control is by serial interface, if high then device control is by parallel interface 24 SDI/DNA Digital IP Serial interface: Parallel interface: 25 SCK/RNW Digital IP Serial interface: Parallel interface: serial interface input data signal high = data, low = address serial interface clock signal high = OP[9:2] is output bus low = OP[9:2] is input bus 26 27 RLC VSMP Digital IP Digital IP Selects whether reset level clamp is applied on a pixel-by-pixel basis. If RLC is required on each pixel then this pin can be tied high Video sample synchronisation pulse. This signal is applied synchronously with MLCK to specify the point in time that the input is sampled. The timing of internal multiplexing between the R, G and B channels is derived from this signal Master clock. This clock is applied at eight, six, three or two times the input pixel rate depending on the operational mode. MCLK is divided internally to define the ADC sample rate and to provide the clock source for digital logic
28
MCLK
Digital IP
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Production Data
WM8143-10
NAME
DGND nc nc DVDD Digital supply
PIN
29 30 31 32
TYPE
Digital supply Digital ground (0V)
DESCRIPTION
Reserved, pin must be left unconnected Reserved, pin must be left unconnected Positive digital supply (5V)
Typical Performance
AVDD = DVDD = 5V, TA = 25 C
o
WM8143-10 DNL 2 1.5 1 0.5 LSB's 0 -0.5 -1 -1.5 -2 0 256 512 ADC Code 768 1024
PGA Gain Code vs Actual Gain
8.25 8 7.75 7.5 7.25 7 6.75 6.5 6.25 6 5.75 5.5 5.25 5 4.75 4.5 4.25 4 3.75 3.5 3.25 3 2.75 2.5 2.25 2 1.75 1.5 1.25 1 0.75 0.5 0.25 0
PGA Gain Code
RED GREEN BLUE
0
1
2
3
4
Actual Gain
5
6
7
8
9
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System Description
COLOUR CCD SENSOR BUFFERING FOR CCD
Production Data
RED RINP OP[9:0] PARALLEL DATA I/O
WM8143-10
GREEN GINP OEB SDI/DNA SCK/RNW SEN/STB NRESET CONTROL/SERIAL DATA IN
BLUE BINP
VSMP MCLK RLC
ANALOGUE INTERFACE TIMING
Figure 1 System Diagram The WM8143-10 signal processing IC interfaces typically via buffering and AC coupling to the output of CCD image sensors. The WM8143-10 also interfaces to CIS image sensors via DC coupling. Analogue output signals from the image sensor are sampled, amplified and offset-corrected by the IC before being converted into digital form by an on-board high-speed 10-bit resolution analogue to digital converter. Figure 1 illustrates a typical system implementation where the three colour outputs from the CCD image sensor are buffered and AC coupled to the analogue inputs of the WM8143-10. The digital interface to the WM8143-10 can be divided into three distinct sections: * * * Parallel Data I/O Digital Control/Serial Timing Analogue Interface Timing
These sections are constructed for ease of use by the system designer and are described in detail on the following pages of this datasheet.
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WM8143-10
Table 1 illustrates the PGA Gains Register codes required for typical gains. (See Typical Performance Graphs). The typical gain may also be calculated using the following equation: Typical Gain = 0.5+(Code0.25).
Device Description
S/H, Offset DACs and PGA
Each analogue input (RINP, GINP, BINP) of the WM8143-10 consists of a sample and hold, a programmable gain amplifier, and a DC offset correction block. The operation of the red input stage is summarised in Figure 2.
RINP
CODE 00000
TYPICAL GAIN 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 3.75 4 4.25
CODE 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
TYPICAL GAIN 4.5 4.75 5 5.25 5.5 5.75 6 6.25 6.5 6.75 7 7.25 7.5 7.75 8 8.25
S/H
+
GAIN=G
VS
+
+
00001
VADC
S/H
VOFFSET VMID
00010 00011 00100 00101 00110 00111 01000 01001 01010 01011
VVS
VMID
RS
Figure 2 Operation of Red Input Stage The sample/hold block can operate in two modes of operation, CDS (Correlated Double Sampling) or Single Ended. In CDS operation the video signal processed is the difference between the voltage applied at the RINP input when RS occurs, and the voltage at the RINP input when VS occurs. This is summarised in Figure 3.
VRS
01100 01101 01110 01111
RS
VS
Figure 3 Video Signal Processed in CDS mode When using CDS the actual DC value of the input signal is not important, as long as the signal extremes are maintained within 0.5 volts of the chip power supplies. This is because the signal processed is the difference between the two sample voltages, with the common DC voltage being rejected. In Single Ended operation, the VS and RS control signals occur simultaneously, and the voltage applied to the reset switch is fixed at VMID. This means that the voltage processed is the difference between the voltage applied to RINP when VS/RS occurs, and VMID. When using Single Ended operation the DC content of the video signal is not rejected. The Programmable Gain Amplifier block multiplies the resulting input voltage by a value between 0.5 and 8.25 which can be programmed independently for each of the three input channels via the serial (or parallel) interface.
Table 1 Typical Gain The DC value of the gained signal can then be trimmed by the 8 bit plus sign DAC. The voltage output by this DAC is shown as VOFFSET in Figure 2. The range of the DAC is (VMID/2) or 1.5*(VMID/2) if the DAC_RANGE bit in Set-up Register 4 is set. The output from the offset DAC stage is referenced to the VMID voltage. This allows the input to the ADC to maximise the dynamic range, and is shown diagrammatically in Figure 2 by the final VMID addition.
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WM8143-10
For the input stage, the final analogue voltage applied to the ADC can be expressed as:
VADC = G * (VVS - VRS) + [(1 - 2 * DSIGN) * DAC_CODE 255 * VMID 2
Production Data
dependent on the type of sampling selected and the polarity of the input video signal.
] + VMID
MCLK VSMP VS CL
Where VADC is the voltage applied, to the ADC G is the programmed gain VVS is the voltage of the video sample. VRS is the voltage of the reset sample, DSIGN is the Offset DAC sign bit DAC_CODE is the offset DAC value. VMID is the WM8143-10 generated VMID voltage. The ADC has a lower reference of VRB (typically 1.5 V) and an upper reference of VRT (typically 3.5 V). When an ADC input voltage is applied to the ADC equal to VRB the resulting code is 000(hex). When an ADC input voltage is applied to the ADC equal to VRT the resulting code is 3FF(hex). Reset Level Clamp Both CDS and Single Ended operation can be used with Reset Level Clamping. A typical input configuration is shown in Figure 4.
00
RS CL 01 (default) RS CL
10
RS CL 11 RS
Figure 5 Reset Sample and Clamp Timing For CDS operation it is important to match the clamp voltage to the amplitude and polarity of the video signal. This will allow the best use of the wide input common-mode range offered by the WM8143-10. If the input video is positive going it is advisable to clamp to VCL (Lower clamp voltage). If the video is negative going it is advisable to clamp to VCU (Upper clamp voltage). Regardless of where the video is clamped the offset DAC is programmed to move the ADC output corresponding to the reset level to an appropriate value to maximise the ADC dynamic range. For Single Ended operation it is recommended that the clamp voltage is set to VCM (middle clamp voltage).
WM8143-10
RINP Cin VS
S/H
+
Gain=G
S/H
RS VRLC VMID
-
Figure 4 Typical Input Configuration Using Reset Level Clamping The position of the clamp relative to the video sample is shown diagramatically in Figure 6 and is programmable by CDSREF1-0 (see Table 6). By default, the reset sample occurs on the fourth MCLK rising edge after VSMP. The relative timing between the reset sample (and CL) and video sample can be altered as shown in Figure 5. When the clamp pulse is active the voltage on the WM8143-10 side of Cin, i.e. RINP, will be forced to be equal to the VRLC clamp voltage. The VRLC clamp voltage is programmable to three different levels via the serial interface. The voltage to which the clamp voltage should be programmed is
VIDEO INPUT
CLAMP PULSE
Figure 6 Position of Clamp Relative to Video Input A reset level clamp is activated if the RLC pin is high on an MCLK rising edge (Figure 7). By default this initiates an internal clamp pulse three MCLK pulses later (shown as CL in Figure 5). The relationship between CL and RS is fixed. Therefore altering the RS position also alters the CL position (Figure 5). Table 6 shows the three possible voltages to which the reset level can be clamped. PD Rev 3f June 98
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WM8143-10
to 4 MSPS. This is achieved by altering the MCLK:VSMP ratio to 3:1. In this mode, the timing of RS and CL must be fixed (refer to Table 3). The sampled video data will pass through the internal pipeline and emerge on the OP[9:0] bus.
MCLK
VSMP
RLC
1
X
X
0
X
X
0
X
Input video
r,g,b
r,g,b
RLC on this pixel
r,g,b
No RLC on this pixel
Max. Speed Monochrome Mode (Mode 4) Figure 12 summarises the timing relationships. This mode allows the maximum sample rate to be increased to 6 MSPS. This is achieved by altering the MCLK:VSMP ratio to 2:1. The latency through the device is identical to modes 1 and 2. CDS is not available in this mode. Slow Colour Mode (Mode 5) Figure 13 summarises the timing relationships. This mode is identical to Mode 1 except that the MCLK to VSMP ratio is 8 : 1 and the maximum sample rate is 1.5 MSPS. To obtain a ratio of 4:4 between the video sample position and the reset sample position, Setup Register 3 CDSREF1-0 control bits b[5:4] should be set to 10. The first three of the four output words are valid. Slow Monochrome Mode (Mode 6) Figure 14 summarises the timing relationships. This mode is identical to mode 2 except that the MCLK to VSMP ratio is 8 : 1 and the maximum sample rate is 1.5 MSPS. To obtain a ratio of 4:4 between the video sample position and the reset sample position, Setup Register 3 CDSREF 1-0 control bits b[5:4] should be set to 10. The first of the four output words is the only valid output.
Figure 7 RLC Timing
Video Sampling Options
The WM8143-10 can interface to CCD sensors using six basic modes of operation (summarised in Table 3). Mode configurations are controlled by a combination of control bits and timing applied to MCLK and VMSP pins. The default operational mode is mode 1: colour with CDS enabled. Colour Mode Definitions (Mode 1) Figure 9 summarises the timing relationships. MCLK is applied at twice the required ADC conversion rate. Synchronisation of sampling and channel multiplexing to the incoming video signal is performed by the VSMP pulse (active high). The three input channels (R,G,B) are sampled in parallel on the rising edge of MCLK following a VSMP pulse. The sampled data is multiplexed into a single data stream at three times the VSMP rate, passes through the internal pipeline and emerges on the OP[9:0] bus. Both Correlated Double Sampling (CDS) and Single Ended Sampling modes of operation are available. Monochrome Mode Definitions One input channel is continuously sampled on the rising edge of MCLK following a VSMP pulse. The user can specify which input channel (R,G,B) is to be sampled by writing to the WM8143-10 internal control registers. There are four separate monochrome modes with different maximum sample rates and CDS availability. Monochrome Mode (Mode 2) Figure 10 summarises the timing relationships. The timing in this mode is identical to mode 1 except that one input channel is sampled three times (due to the multiplexer being held in one position) and passes through the device as three separate samples. The last two samples can be ignored at the output OP[9:0]. Fast Monochrome Mode (Mode 3) Figure 11 summarises the timing relationships. This mode allows the maximum sample rate to be increased
Input Impedance
The input impedance of the WM8143-10 is dependent upon the sampling frequency of the input signal and the gain that the PGA is set to. This is due to the effective capacitance of the `sample and hold' circuits (Figure 8).
S/H RINP/VMID C VMID PGA
VS/RS
Figure 8 Input Impedance S/H Circuit When the VS/RS control is activated the switch closes and the effective impedance of the input is 1/CF where the value of C changes from 0.3pF for minimum gain to PD.Rev 3f June 98
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WM8143-10
9.6pF for maximum gain and F is the sample frequency in Hz. Table 2 illustrates the maximum and minimum input impedance at different frequencies. SAMPLING FREQUENCY (MHz)
0.5 1 2 4 6
Production Data
IMPEDANCE (M ) MIN. GAIN
6.6 3.3 1.6 0.8 0.5
IMPEDANCE (K ) MAX. GAIN
208 104 52 26 17
Table 2 Effects of Frequency on Input Impedance
Calibration
To achieve optimum performance of the WM8143-10, a calibration procedure must be implemented. This is achieved by using a combination of the gain and offset functions to amplify and shift the input signal so that it lies within and maximises the input ADC range.
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WM8143-10
CDS AVAILABLE
Yes
MODE
DESCRIPTION
MAX. SAMPLE RATE
2MSPS
SENSOR INTERFACE DESCRIPTION
TIMING REQUIREMENTS
MCLK max. 12MHz. MCLK: VSMP ratio is 6:1
REGISTER CONTENTS WITH CDS
Setup Reg. 1: 03(H)
REGISTER CONTENTS WITHOUT CDS*
Setup Reg. 1: 01(H)
1
Colour
Three input channels (R, G, B) are sampled in parallel at max. 2MSPS. The sampled data is multiplexed into a single data stream before the internal ADC, giving an internal serial rate of max. 6MSPS One input channel is continuously sampled. The internal multiplexer is held in one position under control of the user. Identical to Mode 2 except that max. sample rate is 4MSPS
2
Monochrome
Yes
2MSPS
Identical to Mode 1
Setup Reg. 1: 07(H) Setup Reg. 3: bits b[7-6] define which channel is sampled Identical to Mode 2 plus Setup Reg. 3: bits b[5-4] must be set to 00(H) Not applicable
Setup Reg. 1:05(H) Setup Reg. 3: bits b[7-6] define which channel is sampled Identical to Mode 2
3
Fast Monochrome
Yes
4MSPS
MCLK max. 12MHz. MCLK: VSMP ratio is 3:1 MCLK max. 12MHz. MCLK: VSMP ratio is 2:1
4
Max. Speed Monochrome
No
6MSPS
Identical to Mode 2 except that max. sample rate is 6MSPS
Setup Reg. 1:45(H) Setup Reg. 3: bits b[7-6] define which channel is sampled Identical to Mode 1
5
Slow Colour
Yes
1.5MSPS
Identical to Mode 1 except that max. sample rate is 1.5MSPS Identical to Mode 2 except that max. sample rate is 1.5MSPS
MCLK max. 12MHz. MCLK: VSMP ratio is 8:1 MCLK max. 12MHz. MCLK: VSMP ratio is 8:1
Identical to Mode 1
6
Slow Monochrome
Yes
1.5MSPS
Identical to Mode 2
Identical to Mode 2
* Only indicates relevant register bits
Table 3 WM8143-10 Mode Summary
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MCLK
Production Data
INPUT
SIGNALS
VSMP
Input r1,g1,b1 video
r2,g2,b2
r3,g3,b3
r4,g4,b4
r5,g5,b5
2
RS INTERNAL SIGNALS
3
4
5
1
2
3
4
5
VS
b0 r1 g1
ADC input
b1
r2
g2
b2
r3
g3
b3
r4
g4
b4
ADC sample
16.5 MCLK periods
OUTPUT OP[9:0] SIGNALS
r1
g1
b1
Figure 9 Default Timing in CDS Colour Mode (Mode 1)
MCLK
INPUT SIGNALS
VSMP
Input r1,g1,b1 video
r2,g2,b2
r3,g3,b3
r4,g4,b4
r5,g5,b5
2
3
4
5
INTERNAL SIGNALS
RS
1 2
3
4
5
VS
X r1 X
ADC input
X
X
X
X
X
X
X
ADC sample
16.5 MCLK periods
OUTPUT
OP[9:0] *
X
X
X
X
X
X
r1
X
X
X
SIGNALS
* This example shows function when Red channel selected. 'X' indicates don't care
Figure 10 Default Timing in CDS Monochrome Mode (Mode 2)
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WM8143-10
MCLK
INPUT SIGNALS
VSMP
Input video
n
n+1
RS
INTERNAL SIGNALS
VS
n
ADC input
ADC sample 23.5 MCLK periods
OUTPUT SIGNALS
OP[9:0]
* This example shows function when Red channel selected.
n
Figure 11 Default Timing in Fast CDS Monochrome Mode (Mode 3)
MCLK
INPUT SIGNALS VSMP
Input video
n
INTERNAL SIGNALS VS
ADC input
1
n
ADC sample 16.5 MCLK periods
OUTPUT
OP[9:0]
n
SIGNALS
* This example shows function when Red channel selected.
Figure 12 Default Timing in Max. Speed non-CDS Monochrome Mode (Mode 4)
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Production Data
INPUT
MCLK
SIGNALS
VSMP
Input r1,g1,b1 video
r2,g2,b2
r3,g3,b3
r4,g4,b4
r5,g5,b5
2
3
4
5
INTERNAL SIGNALS
RS
1
2
3
4
5
VS
g1 b1
X r2 g2 X
ADC input
b0
r1
b2
r3
g3
b3
X
r4
g4
b4
X
ADC sample
16.5 MCLK periods
OUTPUT OP[9:0] SIGNALS
'X' indicates an invalid output
r1
g1
b1
X
Figure 13 Default Timing in Slow CDS Colour Mode (Mode 5)
INPUT
MCLK
SIGNALS
VSMP
Input r1,g1,b1 video
r2,g2,b2
r3,g3,b3
r4,g4,b4
r5,g5,b5
2
3
4
5
INTERNAL RS SIGNALS
VS
1
2
3
4
5
ADC input
b0
r1
X
X
X
r2
X
X
X
r3
X
X
X
r4
X
X
X
ADC sample
16.5 MCLK periods
OUTPUT OP[9:0] SIGNALS
r1
X
X
X
This example shows function when Red channel selected. 'X' indicated invalid output.
Figure 14 Default timing in Slow Monochrome Mode (Mode 6)
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Production Data
WM8143-10
It is expected that this would be achieved on system power-up by attaching a simple RC network to the NRESET pin. The RC network should delay the set-up on the NRESET pin until the other conditions have been established. This feature is only activated on a hardware reset (using the NRESET pin). The software reset does not sample SEN/STB.
Applications Recommendations
Output Data Interface
By default, data is output from the device as a ten-bit wide word on OP[9:0]. Optionally, data can be output in an eight-bit word format. Figure 15 shows this function. Data is presented on pins OP[9:2] at twice pixel rate. In mode 3, the output is spread over three MCLK periods. The first two periods contain byte A data and the third period has byte B data. Either of the two byte A data periods are valid.
Controlling the WM8143-10
The WM8143-10 can be configured through a serial interface or a parallel interface. Selection of the interface type is by the SEN/STB pin which must be tied high (parallel) or low (serial) as shown in Table 4. Serial Interface
MCLK
OP[9:2]
A
B
Figure 15 Eight-bit Multiplexed Bus Output * * * * A =d9,d8,d7,d6,d5,d4,d3,d2 - First byte B =d1,d0,X,X,PNS,CC1,CC0,ORNG - Second byte PNS : This bit shows if the device is configured in parallel or serial mode. 1 = Parallel, 0 = Serial. CC1/CC0 : These bits show which channel the current output was taken from. 00 = RED, 01 = GREEN, 10 = BLUE. ORNG : This bit indicates if the current output pixel has exceeded the maximum or minimum range during processing. 1 = out of range, 0 = within range. X: This is an invalid output.
The serial interface consists of three pins (refer to Figure 16). A six-bit address is clocked in MSB first followed by an eight-bit data word, also MSB first. Each bit is latched on the rising edge of SCK. Once the data has been shifted into the device, a pulse is applied to SEN to transfer the data to the appropriate internal register. Parallel Interface The parallel interface uses bits [9:2] of the OP bus as well as the STB, DNA and RNW pins (refer to Figure 17). Pin RNW must be low during a write operation. The DNA pin defines whether the data byte is address (low) or data (high). The data bus OP[9:2] is latched in during the low period of STB.
*
Internal Register Definition
Table 5 summarises the internal register content. The first 5 addresses in the table are used to program setup registers and to provide a software reset feature (00H is reserved). The remaining 3 entries in the table define the address location of internal data registers. In each case, a further three sub-addresses are defined for the red, green and blue register. Selection between the red, green and blue registers is performed by address bits a1 and a0, as defined in the table. Setting both a1 and a0 equal to 1 forces all three registers to be updated to the same data value. Blank entries in Table 5 should be programmed to zero.
SCK SDI SEN
a5 a4 a3 a2 a1 a0 b7 b6 b5 b4
*
Control Interface Selection
WM8143-10 can be controlled via a serial or parallel interface. The decision on which interface is to be used is made on the sense of the SEN/STB pin on the rising edge of the NRESET signal. SEN/STB
0 1
CONDITION
NRESET rising edge NRESET rising edge
MODE
Serial Interface Parallel Interface
Table 4 WM8143-10 Interface Set-up
b3 b2 b1 b0
Address
Data Word
Figure 16 Serial Interface Timing
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Figure 17 Parallel Interface Timing
STB
OP[9:2]
Production Data
Address
Data
DNA
RNW
ADDRESS
DESCRIPTION
DEFAULT (HEX)
BIT b7 b6 b5 b4 b3 b2 b1 b0
000000 000001
Reserved Setup Register 1 03 VSMP6M MONO CDS ENADC
000010
Setup Register 2
00
INVOP
MUXOP
000011
Setup Register 3
11
CHAN[1]
CHAN[0] CDSREF[1] CDSREF[0]
RLC[1]
RLC[0]
000100 000101 1000a1a0 1001a1a0 1010a1a0
Software Reset Setup Register 4 DAC Values DAC Signs PGA Gains
00 00 00 00 00 PGA[4] PGA[3] PGA[2] PGA[1] DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DACRNG DAC[1] DAC[0] DSIGN PGA[0]
ADDRESS LSB DECODE
Red Register Green Register Blue Register Red, Green and Blue
a1
0 0 1 1
a0
0 1 0 1
Table 5 Register Map Contents
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WM8143-10
BIT NO
0 1
REGISTER
Setup Register 1 Address , 000001
BIT NAMES(S)
ENADC CDS
DEFAULT
1 1
DESCRIPTION
ADC Standby Control: 0 = Standby, 1 = Active Correlated Double Sampling Mode: 0 = Single Ended Mode, 1 = CDS Mode
2
MONO
0
Mono/Colour Select: 0 = Colour, 1 = Monochrome Operation
6 Setup Register 2 Address , 000010 Setup Register 3 Address , 000011
VSMP6M
0
Required when operating in Mode 4: 0 = Other Modes, 1 = Mode 4
0 2 1-0
MUXOP INVOP RLC1-0
0 0 01
Eight Bit Output Mode: 0 = 10-bit, 1 = 8-bit Multiplexed Inverts ADC Output: 0 = Non-inverting, 1 = Inverting Reset Level Clamp Voltage: 00 = 1.5V 01 = 2.5V 10 = 3.5V 11 = Reserved
5-4
CDSREF1-0
01
CDS Mode Reset Timing Adjust: 00 = Advance 1 MCLK Period 01 = Normal 10 = Retard 1 MCLK Period 11 = Retard 2 MCLK Periods
7-6
CHAN1-0
00
Monochrome Mode Channel Select: 00 = Red channel 01 = Green channel 10 = Blue channel 11 = Reserved
Setup Register 4 Address , 000101
1
DACRNG
0
Offset DAC Output Range: 0 = DAC Output Range = Vmid/2 = +/-1.25V 1 = DAC Output Range = 1.5 (Vmid/2) = +/-1.875V
Table 6 Control Bit Descriptions
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Detailed Timing Diagrams
MCLK
tDSU
tDH
Production Data
tDSU
tDH
VSMP, RLC
tVSU tVH
R,G,B Video Inputs (Default Mode)
tVSU tVH
tVSU tVH
R,G,B Video Inputs (CDSREF[1]=0,CDSREF[0]=0)
tVSU
tVH
tRSU tRH tVSU tVH
R,G,B Video Inputs (CDSREF[1]=0,CDSREF[0]=1)
tVSU
tVH
tRSU tRH
tVSU
tVH
R,G,B Video Inputs (CDSREF[1]=1,CDSREF[0]=0)
tVSU
tVH
R,G,B Video Inputs (CDSREF[1]=1,CDSREF[0]=1)
tRSU
tVSU tRH
tVH
tRSU
tRH
Figure 18 Detailed Video Input Timing - Modes 1 and 2
MCLK
tDSU
tDH
tDSU
tDH
VSMP, RLC
tVSU
tVH
tVSU
tVH
R,G,B Video Inputs (CDSREF[1]=0,CDSREF[0]=0)
tRSU tRH
Figure 19 Detailed Video Input Timing - Mode 3
MCLK
tDSU
tDH
VSMP, RLC
tVSU
tVH
tVSU
tVH
R,G,B Video Inputs
RESET
VIDEO
Figure 20 Detailed Video Input Timing - Mode 4
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Production Data
WM8143-10
MCLK
tDSU
tDH
tDSU
tDH
VSMP, RLC
tVSU tVH
tVSU tVH
R,G,B Video Inputs (CDSREF[1]=0,CDSREF[0]=0) R,G,B Video Inputs (CDSREF[1]=0,CDSREF[0]=0)
tVSU
tVH
tRSU tRH
tVSU
tVH
tVSU
tVH
tRSU tRH
R,G,B Video Inputs (CDSREF[1]=0,CDSREF[0]=0) R,G,B Video Inputs (CDSREF[1]=0,CDSREF[0]=0)
tVSU
tVH
tVSU
tVH
tRSU
tRH
tVSU
tVH
tRSU
tRH
Figure 21 Detailed Video Timing - Modes 5 and 6
tCKH tPER tCKL
MCLK
tDSU tDH
VSMP, RLC
tPD
OP[9:0]
RED
GREEN
BLUE
Figure 22 Detailed Digital Timing - Modes 1 and 2
tCKH tPER
tCKL
MCLK
tDSU tDH tDSU tDH
VSMP, RLC OP[9:0]
t PD
tPD
Figure 23 Detailed Digital Timing - Mode 3
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WM8143-10
tCKH tPER tCKL
Production Data
MCLK
tDS U tD H t PD tDS U tPD tD H
VSMP, RLC OP[9:0]
Figure 24 Detailed Digital Timing - Mode 4
tCKH tPER
tCKL
MCLK
tDSU tDH
VSMP, RLC
tPD
OP[9:0]
X
RED
GREEN
BLUE
X
'X' Indicates Invalid Output
Figure 25 Detailed Digital Timing - Modes 5 and 6
tSPER tSCKH tSCKL
SCK
tSSU tSH
SDI
tSCE tSEW tSEC
SEN
Figure 26 Detailed Timing Diagram for Serial Interface
tSTB tSTB
STB OP[9:2] DNA RNW
tOPZ
tASU
tAH
tDSU
tDH
Data Out
Z
tADLS
Address In
tADLH tADHS
Data In
tADHH
Z
Data Out
tOPD
Figure 27 Detailed Timing Diagram for Parallel Interface
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Production Data
WM8143-10
SDI/DNA SEN/STB
Applications Diagram
BINP VRLC VMID GINP RINP OEB + 22 F 24 23 22 21 20 19 18 17 VRT SCK/RNW RLC VSMP MCLK DGND DVDD 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 16 15 14 VRB VRU AGND AVDD NRESET OP[9] OP[8] 100nF + 10F 100nF + 10 F 100nF + 10F 100nF + 10F 100nF 100nF AVDD + 10 F
WM8143-10
13 12 11 10 9
nc nc
DVDD
+ 10F OP[2] OP[3] OP[4] OP[5] OP[6] OP[0] OP[1]
100nF
DGND
Note: AGND and DGND should be starpointed as close as possible to the AGND pins
OP[7]
AGND
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WM8143-10
Package Dimensions
0.80 BSC 0.45 0.30 0.20 M
Production Data
24
17
25
16
32
9
0.20 0.09 1 8
7.00 BSC 9.00 BSC 0.25 1.45 1.35 0.15 0.05 0.75 0.45 Seating Plane
Gauge Plane
0o - 7o
1.60MAX
0.10 DM002.a 32-pin TQFP
Notes: A. All linear dimensions are in milimeters B C The drawing is subject to change without notice Falls within JEDEC MS-026. Refer to this specification for further details.
Last page of WM8143-10 Datasheet
Wolfson Microelectronics
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PD Rev 3f June 98

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